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flash memory 1 k9wag08u1b advance samsung confidential k9k8g08u0b k9wag08u1b * samsung electronics reserves the right to c hange products or specification without notice. information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about samsu ng products, contact your nearest samsung office. 2. samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. k9k8g08u0b
flash memory 2 k9wag08u1b advance samsung confidential k9k8g08u0b document title 1g x 8 / 2g x 8 bit nand flash memory revision history the attached data sheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung elec tronics will evaluate and reply to your requests and questions about device. if you h ave any questions, please contact the samsung branch office near your office. revision no 0.0 0.1 remark advance advance history 1. initial issue 1. k9k8g08u0b-p is added. draft date jun. 11, 2008 jul. 10, 2008
flash memory 3 k9wag08u1b advance samsung confidential k9k8g08u0b general description features ? voltage supply - 3.3v (2.70v ~ 3.60v) ? organization - memory cell array : - k9k8g08u0b : (1g + 32m) x 8bit - k9wag08u1b : (2g + 64m) x 8bit - data register : (2k + 64) x 8bit ? automatic program and erase - page program : (2k + 64)byte - block erase : (128k + 4k)byte ? page read operation - page size : (2k + 64)byte - random read : 25 s(max.) - serial access : 25ns(min.) 1g x 8 / 2g x 8 bit nand flash memory ? fast write cycle time - page program time : 200 s(typ.) - block erase time : 1.5ms(typ.) ? command/address/data multiplexed i/o port ? hardware data protection - program/erase lockout during power transitions ? reliable cmos floating-gate technology - endurance : 100k program/erase cycles ( with 1bit/528byte ecc) - data retention : 10 years ? command driven operation ? unique id for copyright protection ? package : - k9k8g08u0b-pcb0/pib0 48 - pin tsop i (12 x 20 / 0.5 mm pitch) - k9wag08u1b-pcb0/pib0 48 - pin tsop i (12 x 20 / 0.5 mm pitch) - k9wag08u1b-icb0/iib0 52 - pin ulga (12 x 17 / 1.0 mm pitch) offered in 1g x 8bit, the k9k8g08u0b is a 8g-bit nand flash memory with spare 256m-bit. a nd the k9wag08u1b is a 16g-bit nand flash memory with spare 512m-bit. its na nd cell provides the most cost-effecti ve solution for the solid state application mar- ket. a program operation can be performed in typical 200 s on the (2k+64)byte page and an erase operation can be performed in typical 1.5ms on a (128k+4k)byte block. data in the data register can be read out at 25ns cycle time per byte. the i/o pins ser ve as the ports for address and data input/output as well as command i nput. the on-chip write controll er automates all program and er ase functions including pulse repetition, where r equired, and internal verification and marg ining of data. even the write-intensive systems can take advantage of the k9k8g08u0b/k9wag08u1b s extended reliability of 100k program/e rase cycles by providing ecc(error correcting code) with real time mappi ng-out algorithm. the k9k8g08u0b/k9wag08u1 b is an optimum solution for large nonvola- tile storage applications such as solid state file storage and other portable applications requiring non-volatility. product list part number vcc range organization pkg type k9 k8 g08u0b-p 2.70 ~ 3.60v x8 tsop1 k9 wa g08u1b-p k9 wa g08u1b-i 52ulga
flash memory 4 k9wag08u1b advance samsung confidential k9k8g08u0b pin configuration (tsop1) k9k8g08u0b-pcb0/pib0 package dimensions 48-pin lead free plastic thin small out-line package type(i) 48 - tsop1 - 1220f unit :mm/inch 0.787 0.008 20.00 0.20 #1 #24 0.20 +0.07 -0.03 0.008 +0.003 -0.001 0.50 0.0197 #48 #25 0.488 12.40 max 12.00 0.472 0.10 0.004 max 0.25 0.010 () 0.039 0.002 1.00 0.05 0.002 0.05 min 0.047 1.20 max 0.45~0.75 0.018~0.030 0.724 0.004 18.40 0.10 0~8 0.010 0.25 typ 0.125 +0.075 0.035 0.005 +0.003 -0.001 0.50 0.020 () 48-pin tsop1 standard type 12mm x 20mm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 n.c n.c n.c n.c n.c n.c r/b re ce n.c n.c vcc vss n.c n.c cle ale we wp n.c n.c n.c n.c n.c n.c n.c n.c n.c i/o7 i/o6 i/o5 i/o4 n.c n.c n.c vcc vss n.c n.c n.c i/o3 i/o2 i/o1 i/o0 n.c n.c n.c n.c
flash memory 5 k9wag08u1b advance samsung confidential k9k8g08u0b pin configuration (tsop1) k9wag08u1b-pcb0/pib0 package dimensions 48-pin lead free plastic thin small out-line package type(i) 48 - tsop1 - 1220f unit :mm/inch 0.787 0.008 20.00 0.20 #1 #24 0.20 +0.07 -0.03 0.008 +0.003 -0.001 0.50 0.0197 #48 #25 0.488 12.40 max 12.00 0.472 0.10 0.004 max 0.25 0.010 () 0.039 0.002 1.00 0.05 0.002 0.05 min 0.047 1.20 max 0.45~0.75 0.018~0.030 0.724 0.004 18.40 0.10 0~8 0.010 0.25 typ 0.125 +0.075 0.035 0.005 +0.003 -0.001 0.50 0.020 () 48-pin tsop1 standard type 12mm x 20mm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 n.c n.c n.c n.c n.c r/b2 r/b1 re ce1 ce2 n.c vcc vss n.c n.c cle ale we wp n.c n.c n.c n.c n.c n.c n.c n.c n.c i/o7 i/o6 i/o5 i/o4 n.c n.c n.c vcc vss n.c n.c n.c i/o3 i/o2 i/o1 i/o0 n.c n.c n.c n.c
flash memory 6 k9wag08u1b advance samsung confidential k9k8g08u0b 1.00 1.00 1.00 1.00 2.00 7 6 5 4 3 2 1 1.00 1.00 1.00 12.00 0.10 #a1 17.00 0.10 17.00 0.10 b a 12.00 0.10 (datum b) (datum a) 12.0 0 10.00 2.50 2.50 2.00 0.50 1.30 a b c d e f g h j k l m n 12- ? 1.00 0.05 41- ? 0.70 0.05 side view 1.0 ( max .) 0.10 c 17.00 0.10 top view bottom view ab c d e f g h j k l m n 7 6 5 4 3 2 1 k9wag08u1b-icb0/iib0 52ulga (measured in millimeters) nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc vcc vcc vss vss vss /re1 /re2 /ce1 /ce2 cle1 cle2 ale1 ale2 /we1 /we2 /wp1 /wp2 r/b1 r/b2 vss io0-1 io0-2 io1-1 io1-2 io2-1 io3-1 io2-2 io3-2 io4-1 io4-2 io5-1 io5-2 io6-1 io6-2 io7-1 io7-2 ? ab c m 0.1 ? ab c m 0.1 package dimensions pin configuration (ulga)
flash memory 7 k9wag08u1b advance samsung confidential k9k8g08u0b pin description note : connect all v cc and v ss pins of each device to common power supply outputs. do not leave v cc or v ss disconnected. pin name pin function i/o 0 ~ i/o 7 data inputs/outputs the i/o pins are used to input command, address and dat a, and to output data during read operations. the i/ o pins float to high-z when the chip is des elected or when the outputs are disabled. cle command latch enable the cle input controls the activating path for comm ands sent to the command register. when active high, commands are latched into the command register through the i/o ports on the rising edge of the we signal. ale address latch enable the ale input controls the activating path for addres s to the internal address registers. addresses are latched on the rising edge of we with ale high. ce / ce 1 chip enable the ce / ce 1 input is the device selection control. when the device is in the busy state, ce / ce 1 high is ignored, and the device does not return to standby mode in program or erase operation. regarding ce / ce 1 control during read operation , refer to ?page read? section of device operation. ce 2 chip enable the ce 2 input enables the second of k9wag08u1b. re read enable the re input is the serial data-out control, and when active drives the data onto t he i/o bus. data is valid trea after the falling edge of re which also increments the internal column address counter by one. we write enable the we input controls writes to the i/o port. commands , address and data are latched on the rising edge of the we pulse. wp write protect the wp pin provides inadvertent program/erase protecti on during power transitions. the internal high volt- age generator is reset when the wp pin is active low. r/b / r/b 1 ready/busy output the r/b / r/b 1 output indicates the status of the device oper ation. when low, it indicates that a program, erase or random read operation is in process and retu rns to high state upon completion. it is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. vcc power v cc is the power supply for device. vss ground n.c no connection lead is not internally connected.
flash memory 8 k9wag08u1b advance samsung confidential k9k8g08u0b 2k bytes 64 bytes figure 1. k9k8g08u0b functional block diagram figure 2. k9k8g08u0b array organization note : column address : starting address of the register. * l must be set to "low". * the device ignores any additional input of address cycles than required. i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 2nd cycle a 8 a 9 a 10 a 11 *l *l *l *l 3rd cycle a 12 a 13 a 14 a 15 a 16 a 17 a 18 a 19 4th cycle a 20 a 21 a 22 a 23 a 24 a 25 a 26 a 27 5th cycle a 28 a 29 a 30 *l *l *l *l *l v cc x-buffers command i/o buffers & latches latches & decoders y-buffers latches & decoders register control logic & high voltage generator global buffers output driver v ss a 12 - a 30 a 0 - a 11 command ce re we cle wp i/0 0 i/0 7 v cc v ss 512k pages (=8,192 blocks) 2k bytes 8 bit 64 bytes 1 block = 64 pages (128k + 4k) byte i/o 0 ~ i/o 7 1 page = (2k + 64)bytes 1 block = (2k + 64)b x 64 pages = (128k + 4k) bytes 1 device = (2k+64)b x 64pages x 8,192 blocks = 8,448 mbits page register ale (8,192m + 256m) bit nand flash array (2,048 + 64)byte x 524,288 y-gating data register & s/a column address row address : page address : a 12 ~ a 17 plane address : a 18 block address : a 19 ~ the last address
flash memory 9 k9wag08u1b advance samsung confidential k9k8g08u0b product introduction the k9k8g08u0b has a 8,448mbit(8,858,370,048 bit) memory or ganized as 524,288 rows(pages) by 2,112x8 columns. spare 64x8 columns are located from column address of 2,048~2,111. a 2,112-by te data register is connected to memory cell arrays accommo- dating data transfer between the i/o buffers and memory during page read and page program operations. the memory array is made up of 32 cells that are serially connected to form a nand struct ure. each of the 32 cells resides in a different page. a block consists of two nand structured strings. a nand structure consists of 32 ce lls. total 1,081,344 nand cells reside in a block. the progra m and read operations are executed on a page bas is, while the erase operati on is executed on a block basis. the memory array con- sists of 8,192 separately erasable 128k-byt e blocks. it indicates that the bit by bi t erase operation is prohibited on the k9k 8g08u0b. the k9k8g08u0b has addresses multiplexed into 8 i/os. this scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining cons istency in system board design. command, address and data are all written through i/o's by bringing we to low while ce is low. those are latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to multiplex command and address respectively , via the i/o pins. some commands require one bus cycle. for example, reset command, status read command, etc require just one cycle bus. some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. the 1,056m byte physical spa ce requires 31 addresses, thereby requiring five cy cles for addressing : 2 cycles of column address, 3 cycles of row address, in t hat order. page read and page program need the same five address cycl es following the required comm and input. in block erase oper- ation, however, only the three row address cycles are used. device operations are selected by writing specific commands into th e command register. table 1 defines the specific commands of the k9k8g08u0b. in addition to the enhanced architecture and interface, the devic e incorporates copy-back program feature from one page to anot her page without need for transporting the data to and from the exter nal buffer memory. since the time-consuming serial access and data-input cycles are removed, system performance for solid-state disk application is significantly increased. the k9wag08u1b is composed of two k9k8g08u0b chips which are selected separately by each ce 1 and ce 2. table 1. command sets note : 1. random data input/output can be executed in a page. 2. interleave-operation between two chips is allowed. it?s prohibited to use f1h and f2h commands for other operations except interleave-operation. 3. any command between 11h and 81h is prohibited except 70h, f1h, f2h and ffh . caution : any undefined command inputs are prohibited except for above command set of table 1. function 1st cycle 2nd cycle acceptable command during busy read 00h 30h read for copy back 00h 35h read id 90h - reset ffh - o page program 80h 10h two-plane page program (3) 80h---11h 81h---10h copy-back program 85h 10h two-plane copy-back program (3) 85h---11h 81h---10h block erase 60h d0h two-plane block erase 60h---60h d0h random data input (1) 85h - random data output (1) 05h e0h read status 70h o chip1 status (2) f1h o chip2 status (2) f2h o
flash memory 10 k9wag08u1b advance samsung confidential k9k8g08u0b the k9k8g08u0b is arranged in four 2gb memory planes. each plane contains 2,048 blocks and 2,112 byte page registers. this allows it to perform simultaneous page program and block erase by selecting one page or block from each plane. the block addres s map is configured so that two-plane program/e rase operations can be executed by dividi ng the memory array into plane 0~1 or pla ne 2~3 separately. for example, two-plane program/erase operation into plane 0 and plan e 2 is prohibited. that is to say, two-plane program/erase oper- ation into plane 0 and plane 1 or into plane 2 and plane 3 is allowed. plane 0 plane 1 plane 2 plane 3 (2048 block) (2048 block) (2048 block) (2048 block) page 0 page 1 page 63 page 62 memory map block 0 page 0 page 1 page 63 page 62 block 1 page 0 page 1 page 63 page 62 block 4096 page 0 page 1 page 63 page 62 block 4097 page 0 page 1 page 63 page 62 block 4094 page 0 page 1 page 63 page 62 block 4095 page 0 page 1 page 63 page 62 block 8190 page 0 page 1 page 63 page 62 block 8191 2112byte page registers 2112byte page registers 2112byte page registers 2112byte page registers page 0 page 1 page 63 page 62 block 2 page 0 page 1 page 63 page 62 block 3 page 0 page 1 page 63 page 62 block 4098 page 0 page 1 page 63 page 62 block 4099 page 0 page 1 page 63 page 62 block 4092 page 0 page 1 page 63 page 62 block 4093 page 0 page 1 page 63 page 62 block 8188 page 0 page 1 page 63 page 62 block 8189
flash memory 11 k9wag08u1b advance samsung confidential k9k8g08u0b dc and operating characteristics (recommended operating cond itions otherwise noted.) note : 1. v il can undershoot to -0.4v and v ih can overshoot to v cc +0.4v for durations of 20 ns or less. 2. typical value is measured at vcc=3.3v, t a =25 c. not 100% tested. 3. the maximum value of k9k8g08u0b -p?s i li and i lo is 40 a , the maximum value of k9k8g08u0b -i?s i li and i lo is 20 a . parameter symbol test conditions min typ max unit operating current page read with serial access i cc 1 trc=25ns ce =v il, i out =0ma -2535 ma program i cc 2- erase i cc 3- stand-by current(ttl) i sb 1ce =v ih , wp =0v/v cc --1 stand-by current(cmos) i sb 2ce =v cc -0.2, wp =0v/v cc -40200 a input leakage current i li v in =0 to vcc(max) - - 40 output leakage current i lo v out =0 to vcc(max) - - 40 input high voltage v ih (1) - 0.8xvcc - vcc+0.3 v input low voltage, all inputs v il (1) - -0.3 - 0.2xvcc output high voltage level v oh i oh =-400 a2.4-- output low voltage level v ol i ol =2.1ma - - 0.4 output low current(r/b )i ol (r/b )v ol =0.4v 8 10 - ma recommended operating conditions (voltage reference to gnd, k9xxg08uxb-xcb0 : t a =0 to 70 c, k9xxg08uxb-xib0 : t a =-40 to 85 c) parameter symbol min typ. max unit supply voltage v cc 2.7 3.3 3.6 v supply voltage v ss 000v absolute maximum ratings note : 1. minimum dc voltage is -0.6v on input/output pins. during transit ions, this level may undershoot to -2.0v for periods <30ns. maximum dc voltage on input/output pins is v cc +0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 2. permanent device damage may occur if absolute maximum rating s are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data shee t. exposure to absolute maximum rating conditions for extended peri ods may affect reliability. parameter symbol rating unit voltage on any pin relative to vss v cc -0.6 to +4.6 v v in -0.6 to +4.6 v i/o -0.6 to vcc+0.3 (<4.6v) temperature under bias k9xxg08uxb-xcb0 t bias -10 to +125 c k9xxg08uxb-xib0 -40 to +125 storage temperature k9xxg08uxb-xcb0 t stg -65 to +150 c k9xxg08uxb-xib0 short circuit current i os 5ma
flash memory 12 k9wag08u1b advance samsung confidential k9k8g08u0b capacitance ( t a =25 c, v cc =3.3v, f=1.0mhz) note : capacitance is periodically sampled and not 100% tested. k9wag08u1b-ixb0?s capacitance(i/o, input) is 20pf. item symbol test condition min max unit k9k8g08u0b k9wag08u1b* input/output capacitance c i/o v il =0v - 20 40 pf input capacitance c in v in =0v - 20 40 pf valid block note : 1. the device may include initial invalid blocks when first shi pped. additional invalid blocks may develop while being used. th e number of valid blocks is presented with both cases of inva lid blocks considered. invalid bloc ks are defined as blocks that contain one or more bad bits. do not erase or pro- gram factory-marked bad blocks. refer to the attached technical notes for appr opriate management of invalid blocks. 2. the 1st block, which is plac ed on 00h block address, is guaranteed to be a valid block up to 1k program/erase cycles with 1 bit/528byte ecc. 3. the number of valid block is on the basis of single pl ane operations, and this may be decreased with two plane operations. * : each k9k8g08u0b chip in the k9wag08u1b has maximun 160 invalid blocks. parameter symbol min typ. max unit k9k8g08u0b n vb 8,028 - 8,192 blocks k9wag08u1b 16,064* - 16,384* ac test condition (k9xxg08uxb-xcb0: t a =0 to 70 c, k9xxg08uxb-xib0:t a =-40 to 85 c ,k9xxg08uxb: vcc=2.7v~3.6v unless otherwise noted) parameter k9wag08u1b input pulse levels 0v to vcc input rise and fall times 5ns input and output timing levels vcc/2 output load 1 ttl gate and cl=50pf (k9k8g08u0b-p/k9wag08u1b-i) 1 ttl gate and cl=30pf (k9wag08u1b-p) mode selection note : 1. x can be v il or v ih. 2. wp should be biased to cmos high or cmos low for standby. cle ale ce we re wp mode hll hx read mode command input l h l h x address input(5clock) hll hh write mode command input l h l h h address input(5clock) l l l h h data input l l l h x data output x x x x h x during read(busy) xxxxxh during program(busy) xxxxxh during erase(busy) x x (1) x x x l write protect xxhxx 0v/v cc (2) stand-by
flash memory 13 k9wag08u1b advance samsung confidential k9k8g08u0b ac timing characteristics for command / address / data input notes : 1. the transition of the corresponding control pins must occur only once while we is held low. 2. tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. parameter symbol min max unit cle setup time t cls (1) 12 - ns cle hold time t clh 5-ns ce setup time t cs (1) 20 - ns ce hold time t ch 5-ns we pulse width t wp 12 - ns ale setup time t als (1) 12 - ns ale hold time t alh 5- ns data setup time t ds (1) 12 - ns data hold time t dh 5-ns write cycle time t wc 25 - ns we high hold time t wh 10 - ns address to data loading time t adl (2) 70 - ns program / erase characteristics note : 1. typical value is measured at vcc=3.3v, t a =25 c. not 100% tested. 2. typical program time is defined as the time within which more than 50% of the whole pages are programmed at 3.3v vcc a nd 25 c tempera- ture . parameter symbol min typ max unit program time t prog - 200 700 s dummy busy time for two-plane page program t dbsy -0.51 s number of partial program cycles nop - - 4 cycles block erase time t bers -1.52 ms
flash memory 14 k9wag08u1b advance samsung confidential k9k8g08u0b ac characteristics for operation note : 1. if reset command(ffh) is written at ready state, the device goes into busy for maximum 5 s. parameter symbol min max unit data transfer from cell to register t r -25 s ale to re delay t ar 10 - ns cle to re delay t clr 10 - ns ready to re low t rr 20 - ns re pulse width t rp 12 - ns we high to busy t wb - 100 ns read cycle time t rc 25 - ns re access time t rea -20ns ce access time t cea -25ns re high to output hi-z t rhz - 100 ns ce high to output hi-z t chz -30ns re high to output hold t rhoh 15 - ns re low to output hold t rloh 5- ns ce high to output hold t coh 15 - ns re high hold time t reh 10 - ns output hi-z to re low t ir 0-ns re high to we low t rhw 100 - ns we high to re low t whr 60 - ns device resetting time(read/program/erase) t rst - 5/10/500 (1) s
flash memory 15 k9wag08u1b advance samsung confidential k9k8g08u0b nand flash technical notes identifying initial invalid block(s) initial invalid block(s) initial invalid blocks are defined as blocks that contain one or more initial inva lid bits whose reliability is not guaranteed by samsung. the information regarding the initial invalid block(s) is called the initial invalid block inform ation. devices with initial in valid block(s) have the same quality level as devices with all valid blocks and have the same ac and dc characteristics. an initial invalid bl ock(s) does not affect the performance of valid bl ock(s) because it is isolated from the bi t line and the common source line by a sele ct tran- sistor. the system design must be able to mask out the initial in valid block(s) via address mappi ng. the 1st block, which is pl aced on 00h block address, is guaranteed to be a valid bl ock up to 1k program/erase cycles with 1bit /528byte ecc. all device locations are erased(ffh) except locations where the initial invalid block( s) information is written prior to shippi ng. the ini- tial invalid block(s) status is defined by the 1st byte in t he spare area. samsung makes sure that either the 1st or 2nd page o f every initial invalid block has non-ffh data at the column address of 2,048. since the initial invalid block information is also eras able in most cases, it is impossible to recover the information once it has been erased. therefore, the system must be able to recogniz e the initial invalid block(s) based on the original initial invalid block information and create the initial invalid block table via the following suggested flow chart(figure 3). any intentional erasure of t he original initial invalid block information is prohibited. * check "ffh" at the column address 2,048 figure 3. flow chart to create initial invalid block table. start set block address = 0 check "ffh" increment block address last block ? end no yes yes create (or update) no initial of the 1st and 2nd page in the block invalid block(s) table
flash memory 16 k9wag08u1b advance samsung confidential k9k8g08u0b nand flash technical notes (continued) program flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 80h write address write data write 10h read status register program completed or r/b = 1 ? program error yes no yes : if program operation r esults in an error, map out the block including the page in error and copy the target data to another block. * error in write or read operation within its life time, additional invalid bl ocks may develop with nand flash memory. refer to the qualification report for the a ctual data.the following possible failure modes shoul d be considered to implement a highly reli able system. in the case of status rea d fail- ure after erase or program, block replac ement should be done. because program status fail during a page program does not affect the data of the other pages in the same block, block replacem ent can be executed with a page-si zed buffer by finding an erased empty block and reprogramming the current target data and copying t he rest of the replaced block. in case of read, ecc must be employed. to improve the efficiency of me mory space, it is recommended that the r ead or verification failure due to single bit error be reclaimed by ecc without any block replac ement. the said additional block failure rate does not include those reclaimed blocks. failure mode detection and countermeasure sequence write erase failure status read after erase --> block replacement program failure status read after program --> block replacement read single bit failure ve rify ecc -> ecc correction ecc : error correcting code --> hamming code etc. example) 1bit correction & 2bit detection
flash memory 17 k9wag08u1b advance samsung confidential k9k8g08u0b erase flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 60h write block address write d0h read status register or r/b = 1 ? erase error yes no : if erase operation results in an error, map out the failing block and replace it with another block. * erase completed yes read flow chart start verify ecc no write 00h write address read data ecc generation reclaim the error page read completed yes nand flash technical notes (continued) write 30h block replacement * step1 when an error happens in the nth page of the bloc k ?a? during erase or program operation. * step2 copy the data in the 1st ~ (n-1)th page to the same location of another free block. (block ?b?) * step3 then, copy the nth page data of the block ?a? in the buffer memory to the nth page of the block ?b?. * step4 do not erase or program to block ?a? by creating an ?invalid block? table or other appropriate scheme. buffer memory of the controller. 1st block a block b (n-1)th nth (page) { 1st (n-1)th nth (page) { an error occurs. 1 2
flash memory 18 k9wag08u1b advance samsung confidential k9k8g08u0b interleave page program k9wag08u1b is composed of two k9k8g08u0bs. and k9k8g08u 0b also is composed of two k9f4g08u0bs. k9k8g08u0b pro- vides interleaving operation between two k9f4g08u0bs. this interleaving page program improves the system throughput almost twice compared to non-interleaving page program. at first, the host issues page program command to one of th e k9f4g08u0b chips, say k9f4g08u0b(chip #1). due to this k9k8g08u0b goes into busy state. during this time, k9f4g08u0b(chi p #2) is in ready state. so it can execute the page program command issued by the host. after the execution of page program by k9f4g08u0b(chip #1), it can execute another page program regardless of the k9f4g08u0b(chip #2). before that the host needs to check the status of k9f4g08u0b(chip #1) by issuing f1h command. only when the status of k9f4g08u0b(chip #1) becomes ready st atus, host can issue another page program command. if the k9f4g08u0b(chip #1) is in busy state, the host has to wa it for the k9f4g08u0b(chip #1) to get into ready state. similarly, k9f4g08u0b chip(chip #2) can execute another page prog ram after the completion of the previous program. the host can monitor the status of k9f4g08u0b(chip #2) by issuing f2h command. when the k9f4g08u 0b(chip #2) shows ready state, host can issue another page program command to k9f4g08u0b(chip #2). this interleaving algorithm improves the system throughput al most twice. the host can issue page program command to each chip individually. this reduces the time lag for the completion of operation. notes : during interleave operations, 70h command is prohibited.
flash memory 19 k9wag08u1b advance samsung confidential k9k8g08u0b r/ b (#1) busy of chip #1 i/o x 80h 10h command a 30 : low add & data 80h 10h a 30 : high add & data busy of chip #2 internal only r/b (#2) internal only r/b interleave page program f1h or f2h ab c d another page program on chip #1 state a : chip #1 is executing a page program operation and chip #2 is in ready state. so the host can issue a page program command to ch ip #2. state b : both chip #1 and chip #2 are executing page program operation. state c : page program on chip #1 is terminated, but page program on chip #2 is still operating. and t he system should issue f1h comman d to detect the status of chip #1. if chip #1 is ready, status i/o6 is "1" and the system can issue another page program command to chip #1. state d : chip #1 and chip #2 are ready. according to the above process, the system can oper ate page program on chip #1 and chip #2 alternately. status operation status command / data f1h f2h a chip 1 : busy, chip 2 : ready 8xh cxh b chip 1 : busy, chip 2 : busy 8xh 8xh c chip 1 : ready, chip 2 : busy cxh 8xh d chip 1 : ready, chip 2 : ready cxh cxh
flash memory 20 k9wag08u1b advance samsung confidential k9k8g08u0b r/ b (#1) busy of chip #1 i/o x 60h d0h command a 30 : low add 60h d0h a 30 : high add busy of chip #2 internal only r/b (#2) internal only r/b interleave block erase f1h or f2h ab c d another block erase on chip #1 state a : chip #1 is executing a block erase operation, and chip #2 is in ready state. so the host can issue a block erase command to chi p #2. state b : both chip #1 and chip #2 are executing block erase operation. state c : block erase on chip #1 is term inated, but block erase on chip #2 is still oper ating. and the system should issue f1h command to detect the status of chip #1. if chip #1 is ready, status i/o6 is "1" and the system can issue another block erase command to chip #1. state d : chip #1 and chip #2 are ready. according to the above process, the system can oper ate block erase on chip #1 and chip #2 alternately. status operation status command / data f1h f2h a chip 1 : busy, chip 2 : ready 8xh cxh b chip 1 : busy, chip 2 : busy 8xh 8xh c chip 1 : ready, chip 2 : busy cxh 8xh d chip 1 : ready, chip 2 : ready cxh cxh
flash memory 21 k9wag08u1b advance samsung confidential k9k8g08u0b r/b (#1) t dbsy i/o x command t prog of chip #1 internal only r/b (#2) internal only r/b 81h 10h a 30 :low add & data 80h 11h a 30 : low add & data f1h or f2h* 81h 10h a 30 :high add & data 80h 11h a 30 : high add & data t dbsy t prog of chip #2 r/nb (#1) i/o x internal only r/b (#2) internal only r/b t prog of chip #2 1 1 interleave two-plane page program state a : chip #1 is executing a page program operation, and chip #2 is in ready state. so the host can issue a page program command to c hip #2. state b : both chip #1 and chip #2 are executing page program operation. state c : page program on chip #1 is completed and chip #1 is ready for the next operation. chip #2 is still executing page program oper ation. state d : both chip #1 and chip #2 are ready. note : *f1h command is required to check the status of chip #1 to issue the next page program command to chip #1. f2h command is required to check the status of chip #2 to issue the next page program command to chip #2. according to the above process, the system can operate tw o-plane page program on chip #1 and chip #2 alternately. ab cd
flash memory 22 k9wag08u1b advance samsung confidential k9k8g08u0b r/b (#1) i/o x command t bers of chip #1 internal only r/b (#2) internal only r/b 60h d0h a 30 :low add 60h a 30 : low add f1h or f2h* 60h d0h a 30 :high add 60h a 30 : high add t bers of chip #2 t bers of chip #2 1 1 interleave two-plane block erase r/b (#1) i/o x internal only r/b (#2) internal only r/b ab c state a : chip #1 is executing a block erase operati on, and chip #2 is in ready state. so the host can issue a block erase command to chi p #2. state b : both chip #1 and chip #2 are executing block erase operation. state c : block erase on chip #1 is completed and ch ip #1 is ready for the next operation. chip #2 is still executing block erase operat ion. state d : both chip #1 and chip #2 are ready. note : *f1h command is required to check the status of chip #1 to issue the next block erase command to chip #1. f2h command is required to check the st atus of chip #2 to issue the nex t block erase command to chip #2. as the above process, the system can operate two-pl ane block erase on chip #1 and chip #2 alternatively. d
flash memory 23 k9wag08u1b advance samsung confidential k9k8g08u0b system interface using ce don?t-care. for an easier system interface, ce may be inactive during the data-loading or serial access as shown below. the internal 2,112byte data registers are utilized as separate buf fers for this operation and the system desig n gets more flexible. in addition, for v oice or audio applications whic h use slow cycle time on the order of -seconds, de-activating ce during the data-loading and serial access would provide significant sa vings in power consumption. figure 4. program operation with ce don?t-care. ce we t wp t ch t cs address(5cycles) 80h data input ce cle ale we data input ce don?t-care 10h address(5cycle) 00h ce cle ale we data output(serial access) ce don?t-care r/b t r re t cea out t rea ce re i/o 0 ~ 7 figure 5. read operation with ce don?t-care. 30h i/ox i/ox
flash memory 24 k9wag08u1b advance samsung confidential k9k8g08u0b command latch cycle ce we cle ale command address latch cycle t cls t cs t clh t ch t wp t als t alh t ds t dh note device i/o data address i/ox data in/out col. add1 col. add2 row add1 row add2 row add3 k9k8g08u0b i/o 0 ~ i/o 7 2,112byte a0~a7 a8~a11 a12~a19 a20~a27 a28~a30 i/ox ce we cle ale col. add1 t cs t wc t wp t als t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t ds t dh t wp i/ox col. add2 row add1 row add2 t wc t wh t alh t als t ds t dh row add3 t alh t cls
flash memory 25 k9wag08u1b advance samsung confidential k9k8g08u0b input data latch cycle ce cle we din 0 din 1 din final ale t als t clh t wc t ch t ds t dh t ds t dh t ds t dh t wp t wh t wp t wp i/ox * serial access cycle after read (cle=l, we =h, ale=l) re ce r/b dout dout dout t rc t rea t rr t rhoh t rea t reh t rea t coh t rhz i/ox t chz t rhz notes : transition is measured at 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. trloh is valid when frequency is higher than 33mhz. trhoh starts to be valid when frequency is lower than 33mhz.
flash memory 26 k9wag08u1b advance samsung confidential k9k8g08u0b status read cycle ce we cle re 70h status output t clr t clh t wp t ch t ds t dh t rea t ir t rhoh t coh t whr t cea t cls i/ox t chz t rhz t cs re ce r/b i/ox t rr t cea t rea t rp t reh t rc t rhz t chz serial access cycle after read (edo type, cle=l, we =h, ale=l) t rhoh t coh t rloh dout dout t rea notes : transition is measured at 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. trloh is valid when frequency is higher than 33mhz. trhoh starts to be valid when frequency is lower than 33mhz.
flash memory 27 k9wag08u1b advance samsung confidential k9k8g08u0b read operation (intercepted by ce ) ce cle r/b we ale re busy 00h dout n dout n+1 dout n+2 row address column address t wb t ar t chz t r t rr t rc 30h read operation ce cle r/b we ale re busy 00h col. add1 col. add2 row add1 dout n dout n+1 column address row address t wb t ar t r t rc t rhz t rr dout m t wc row add2 30h t clr i/ox i/ox col. add1 col. add2 row add1 row add2 row add3 row add3 t c oh
flash memory 28 k9wag08u1b advance samsung confidential k9k8g08u0b random data output in a page ce cle r/b we ale re busy 00h dout n dout n+1 row address column address t w b t ar t r t rr t r c 30h 05h column address dout m dout m+1 i/ox col. add1 col. add2 row add1 row add2 col add1 col add2 row add3 t clr e0h t whr t rea t rhw
flash memory 29 k9wag08u1b advance samsung confidential k9k8g08u0b page program operation ce cle r/b we ale re 80h 70h i/o 0 din n din 10h m serialdata input command column address row address 1 up to m byte serial input program command read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc t wc t wc i/ox co.l add1 col. add2 row add1 row add2 row add3 notes : tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. t adl t whr
flash memory 30 k9wag08u1b advance samsung confidential k9k8g08u0b page program operation with random data input ce cle r/b we ale re 80h 70h i/o 0 din n din 10h m serial data input command column address row address serial input program command read status command t prog t wb t wc t wc 85h random data input command column address t wc din j din k serial input i/ox col. add1 col. add2 row add1 row add2 col. add1 col. add2 row add3 notes : 1. tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. t adl t adl t whr
flash memory 31 k9wag08u1b advance samsung confidential k9k8g08u0b 00h i/o x 85h column address row address read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc busy t wb t r busy 10h copy-back data input command 35h column address row address data 1 data n col add1 col add2 row add1 row add2 col add1 col add2 row add1 row add2 row add3 row add3 70h notes : 1. tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. t adl t whr data 1 data n t rc copy-back program operation with random data input ce cle r/b we ale re i/ox
flash memory 32 k9wag08u1b advance samsung confidential k9k8g08u0b block erase operation ce cle r/b we ale re 60h erase command read status command i/o 0 =1 error in erase d0h 70h i/o 0 busy t wb t bers i/o 0 =0 successful erase row address t wc auto block erase setup command i/ox row add1 row add2 row add3 t whr
flash memory 33 k9wag08u1b advance samsung confidential k9k8g08u0b twhr two-plane page program operation 80h i/o 0 ~ 7 r/b 11h ex.) two-plane page program t dbsy address & data input 81h 10h address & data input 70h t prog col add1,2 & row add 1,2,3 2112 byte data ce cle r/b we ale re 80h din n din 11h m serial data input command column address program tdbsy twb twc command (dummy) din n 10h tprog twb i/o 0 program confirm command (true) 81h 70h page row address i/ox 1 up to 2112 byte data serial input din m read status command t dbsy : typ. 500ns max. 1 s col add1 col add2 row add1 row add2 row add3 col add1 col add2 row add1 row add2 row add3 col add1,2 & row add 1,2,3 2112 byte data a 0 ~ a 11 : valid a 12 ~ a 17 : fixed ?low? a 18 : fixed ?low? a 19 ~ a 29 : fixed ?low? a 0 ~ a 11 : valid a 12 ~ a 17 : valid a 18 : fixed ?high? a 19 ~ a 29 : valid a 30 : valid a 30 :must be same as previous a 30 note: any command between 11h and 81h is prohibited except 70h and ffh. note
flash memory 34 k9wag08u1b advance samsung confidential k9k8g08u0b two-plane block erase operation block erase setup command1 erase confirm command read status command 60h row add1,2,3 i/o 0 ~ 7 r/b 60h a 9 ~ a 25 d0h t bers * for two-plane erase operation, block address to be erased should be repeated before "d0h" command. ex.) address restriction for tw o-plane block erase operation ce cle r/b i/o x we ale re 60h row add1 d0h 70h i/o 0 busy t wb t bers t wc d0h 70h address address row add1,2,3 i/o 0 = 0 successful erase i/o 0 = 1 error in erase row add2 row add3 a 12 ~ a 17 : fixed ?low? a 18 : fixed ?low? a 19 ~ a 29 : fixed ?low? a 12 ~ a 17 : fixed ?low? a 18 : fixed ?high? a 19 ~ a 29 : valid a 30 : valid a 30 : must be same as previous a 30 60h row add1 d0h row add2 row add3 row address t wc block erase setup command2 row address t whr
flash memory 35 k9wag08u1b advance samsung confidential k9k8g08u0b read id operation ce cle we ale re 90h read id command maker code device code 00h ech t rea address 1cycle i/ox t ar device device code(2nd cycle) 3rd cycle 4th cycle 5th cycle k9k8g08u0b dch 51h 95h 58h k9wag08u1b same as k9k8g08u0b device 4th cyc. code 3rd cyc. 5th cyc.
flash memory 36 k9wag08u1b advance samsung confidential k9k8g08u0b 4th id data description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 page size (w/o redundant area ) 1kb 2kb 4kb 8kb 0 0 0 1 1 0 1 1 block size (w/o redundant area ) 64kb 128kb 256kb 512kb 0 0 0 1 1 0 1 1 redundant area size ( byte/512byte) 8 16 0 1 organization x8 x16 0 1 serial access minimum 50ns/30ns 25ns reserved reserved 0 1 0 1 0 0 1 1 id definition table description 1 st byte 2 nd byte 3 rd byte 4 th byte 5 th byte maker code device code internal chip number, cell type, num ber of simultaneously programmed pages, etc page size, block size,redundant area size, or ganization, serial access minimum plane number, plane size 3rd id data description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 internal chip number 1 2 4 8 0 0 0 1 1 0 1 1 cell type 2 level cell 4 level cell 8 level cell 16 level cell 0 0 0 1 1 0 1 1 number of simultaneously programmed pages 1 2 4 8 0 0 0 1 1 0 1 1 interleave program between multiple chips not support support 0 1 cache program not support support 0 1
flash memory 37 k9wag08u1b advance samsung confidential k9k8g08u0b 5th id data description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 plane number 1 2 4 8 0 0 0 1 1 0 1 1 plane size (w/o redundant area) 64mb 128mb 256mb 512mb 1gb 2gb 4gb 8gb 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 reserved 0 0 0
flash memory 38 k9wag08u1b advance samsung confidential k9k8g08u0b device operation page read page read is initiated by writing 00h-30h to the command register along with five address cycles. after initial power up, 00h c ommand is latched. therefore only five address cy cles and 30h command initiates that operation after initial power up. the 2,112 bytes of data within the selected page are transferred to the data registers in less than 20 s(t r ). the system controller can detect the completion of this data transfer(tr) by analyzing the output of r/b pin. once the data in a page is loaded into the data registers, they may be read out in 25ns cycle time by sequentially pulsing re . the repetitive high to low transitions of the re clock make the device output the data starting from the selected column address up to the last column address. the device may output random data in a page instead of the co nsecutive sequential data by writing random data output command. the column address of next data, which is going to be out, ma y be changed to the address which follows random data output com- mand. random data output can be operated multiple time s regardless of how many times it is done in a page. figure 6. read operation address(5cycle) 00h col. add.1,2 & row add.1,2,3 data output(serial access) data field spare field ce cle ale r/b we re t r 30h i/ox
flash memory 39 k9wag08u1b advance samsung confidential k9k8g08u0b figure 7. random data output in a page address 00h data output r/b re t r 30h address 05h e0h 5cycles 2cycles data output data field spare field data field spare field i/ox col. add.1,2 & row add.1,2,3 page program the device is programmed basically on a page basis, but it does allow multiple partia l page programming of a word or consecutiv e bytes up to 2,112, in a single page program cycle. the number of consecutive partial page prog ramming operation within the same page without an intervening erase operation must not exceed 4 ti mes for a single page. the addressing should be done in sequent ial order in a block. a page program cycle consists of a serial data loading period in which up to 2,112bytes of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. the serial data loading period begins by inputting the serial data input command(80h) , followed by the fi ve cycle address input s and then serial data loading. the words other than those to be programmed do not need to be loaded. the device supports random data input in a page. the column address for the next data, which wi ll be entered, may be changed to the address which follows rando m data input command(85h). random data input may be operated multiple times regardless of how many times it is done in a page. the page program confirm command(10h) initiates the programming process. writing 10h alone wit hout previously entering the serial data will not initiate the programming process. the internal write state controller automat ically executes the algorithm s and tim- ings necessary for program and verify, thereb y freeing the system controller for other tasks. once the program process starts, the read status register command may be entered to read the status r egister. the system controller can detect the completion of a p ro- gram cycle by monitoring the r/b output, or the status bit(i/o 6) of the status register. only the read status command and reset command are valid while programming is in progress. when the p age program is complete, the write status bit(i/o 0) may be checked(figure 8). the internal write verify detects only errors for "1"s that are no t successfully programmed to "0"s. the com mand register remains in read status command mode until an other valid command is written to the command register. figure 8. program & read status operation 80h r/b address & data input i/o 0 pass data 10h 70h fail t prog i/ox col. add.1,2 & row add.1,2,3 "0" "1" col. add.1,2
flash memory 40 k9wag08u1b advance samsung confidential k9k8g08u0b figure 9. random data input in a page 80h r/b address & data input i/o 0 pass 10h 70h fail t prog 85h address & data input i/ox col. add.1,2 & row add1,2,3 col. add.1,2 data data copy-back program "0" "1" copy-back program with read for copy-back is configured to qui ckly and efficiently rewrite data stored in one page without data re- loading when the bit error is not in data stored. since the time -consuming re-loading cycles are removed, the system performanc e is improved. the benefit is especially obvious when a portion of a bl ock is updated and the rest of the block also needs to be cop ied to the newly assigned free block. copy-back oper ation is a sequential execution of read fo r copy-back and of c opy-back program wit h the destination page address. a read operation with "35h" command and the address of the source page moves the whole 2,112-byte data into the internal data buffer. a bit error is checked by sequential reading the data output. in the case where there is no bit error, the data do not need to be reloaded. therefore copy-back program operation is initiated by issuing page-copy data-input command (85h) with destination page address. actual programming operation begins after program confirm command (10h) is issued. once the program process starts, the read status register command (70h) may be entered to read the status register. the system contr ol- ler can detect the completion of a program cycle by monitoring the r/b output, or the status bit(i/o 6) of the status register. when the copy-back program is complete, the writ e status bit(i/o 0) may be checked(figure 10 & figure 11). the command register remains in read status command mode until another valid command is written to the command register. during copy-back program, data modifica tion is possible using random data input command (85h) as shown in figure11. figure 10. page copy-back program operation figure 11. page copy-back program operation with random data input note : 1. copy-back program operation is allo wed only within the same memory plane. "0" "1" 00h r/b add.(5cycles) i/o0 pass fail t prog t r source address destination address i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 & row add.1,2,3 35h data output 85h add.(5cycles) 10h 70h r/b source address destination address there is no limitation for the number of repetition. i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 & row add.1,2,3 col. add.1,2 00h add.(5cycles) 35h t r data output 85h add.(5cycles) data 85h add.(2cycles) data 10h t prog 70h
flash memory 41 k9wag08u1b advance samsung confidential k9k8g08u0b figure 12. block erase operation block erase the erase operation is done on a block basis. bl ock address loading is accompli shed in three cycles initiated by an erase setup command(60h). only address a 18 to a 30 is valid while a 12 to a 17 is ignored. the erase confirm command(d0h) following the block address loading initiates the internal erasi ng process. this two-step sequence of se tup followed by execution command ensures t hat memory contents are not accidentally er ased due to external noise conditions. at the rising edge of we after the erase confirm command input, the internal write controller handles er ase and erase-verify. when the erase operation is completed, the write status bit( i/o 0) may be checked. figure 12 details the sequence. 60h row add 1,2,3 r/b address input(3cycle) i/o 0 pass d0h 70h fail t bers i/ox "0" "1" two-plane page program two-plane page program is an extension of page program, for a si ngle plane with 2,112 byte page registers. since the device is equipped with four memory planes, activating the two sets of 2, 112 byte page registers enables a simultaneous programming of tw o pages. but there is some restriction, two-plane program operati ons can be executed by dividing the memory array into plane 0~1 or plane 2~3 separately. for example, two-plane program operation into plane 0 and plane 2 is prohibited. that is to say, two-plan e pro- gram operation into plane 0 and plane 1 or into plane 2 and plane 3 is allowed. after writing the first set of data up to 2,112 byte into the selected page register, dummy page program command (11h) instead of actual page program command (10h) is inputted to finish data-loadi ng of the first plane. since no programming process is involv ed, r/b remains in busy state for a short period of time(tdbsy). r ead status command (70h) may be issued to find out when the device returns to ready state by polling the ready/busy status bit(i/o 6). then the next set of data for the other plane is inputted a fter the 81h command and address sequences. after inputting data for the la st plane, actual true page program(10h) instead of dummy page program command (11h) must be followed to star t the programming process. the operation of r/b and read status is the same as that of page program. althougth two planes are progra mmed simultaneously, pass/fail is not available for each page when the program operation completes. status bit of i/o 0 is set to "1" when any of the pages fails. restriction in addressing with two-pl ane page program is shown is figure13.
flash memory 42 k9wag08u1b advance samsung confidential k9k8g08u0b figure 13. two-plane page program 80h 11h data input plane 0 (2048 block) block 0 block 2 block 4094 block 4092 80h i/o 0 ~ 7 r/b address & data input 11h 81h 10h t dbsy t prog 70h address & data input note : 1. it is noticeable that same row address except for a 18 is applied to the two blocks 81h 10h plane 1 (2048 block) block 1 block 3 block 4095 block 4093 figure 14. two-plane block erase operation 60h i/o x r/b 60h d0h i/o 0 pass fail t bers address (3 cycle) address (3 cycle) 70h "0" "1" a 12 ~ a 17 : fixed ?low? a 18 : fixed ?low? a 19 ~ a 29 : fixed ?low? a 12 ~ a 17 : fixed ?low? a 18 : fixed ?high? a 19 ~ a 29 : valid two-plane block erase basic concept of two-plane block erase operati on is identical to that of two-plane p age program. up to two blocks, one from eac h plane can be simultaneously erased. standard block erase comm and sequences (block erase setup command(60h) followed by three address cycles) may be repeated up to twice for erasing up to two blocks. only one block should be selected from each pla ne. the erase confirm command(d0h) initiates the actual erasi ng process. the completion is detected by monitoring r/b pin or ready/ busy status bit (i/o 6). two-plane erase operations can be execut ed by dividing the memory array into plane 0~1 or plane 2~3 separately. for example, two-plane erase operation into plane 0 and plane 2 is pr ohibited. that is to say, two-plane erase operation into p lane 0 and plane 1 or into plane 2 and plane 3 is allowed. a 0 ~ a 11 : valid a 12 ~ a 17 : fixed ?low? a 18 : fixed ?low? a 19 ~ a 29 : fixed ?low? a 30 : valid a 0 ~ a 11 : valid a 12 ~ a 17 : valid a 18 : fixed ?high? a 19 ~ a 29 : valid a 30 : must be same as previous a 30 a 30 : valid a 30 : must be same as previous a 30 note : it is an example for two-plane page program into plane 0~1(in this case, a 30 is low), and the method for two-plane page program into plane 2 ~3 is same. two-plane page program into plane 0&2(or plane 0&3, or plane 1&2, or plane 1&3) is prohibited. note : two-plane block erase into plane 0&2(or plane 0&3, or plane 1&2, or plane 1&3) is prohibited. 2. any command between 11h and 81h is prohibited except 70h and ffh. note2 a 30 : must be same as previous a 30
flash memory 43 k9wag08u1b advance samsung confidential k9k8g08u0b two-plane copy-back program two-plane copy-back program is an ex tension of copy-back program, for a single pla ne with 2,112 byte page registers. since the device is equipped with four memory planes, activating the two sets of 2,112 byte p age registers enables a simultaneous program - ming of two pages. figure 15. two-plane copy-back program operation 00h r/b add.(5cycles) t r source address on plane0 35h i/ox col. add.1,2 & row add.1,2,3 1 r/b 85h 70h/f1h t prog add.(5cycles) destination address 10h i/ox col. add.1,2 & row add.1,2,3 81h add.(5cycles) destination address col. add.1,2 & row add.1,2,3 11h t dbsy a 0 ~ a 11 : fixed ?low? a 12 ~ a 17 : valid a 18 : fixed ?high? a 19 ~ a 29 : valid a 30 : must be same as previous a 30 1 note2 data field spare field data field spare field (1) (2) (3) (3) plane0 plane1 source page target page source page target page 00h add.(5cycles) source address on plane1 35h col. add.1,2 & row add.1,2,3 t r data output data output a 0 ~ a 11 : fixed ?low? a 12 ~ a 17 : fixed ?low? a 18 : fixed ?low? a 19 ~ a 29 : fixed ?low? a 30 : valid (1) : read for copy back on plane0(or plane2) (2) : read for copy back on plane1(or plane3) (3) : two-plane copy-back program note : 1. copy-back program operation is allowed only within the same memory plane. 2. on the same plane, it?s prohibited to operat e copy-back program from an odd address page(source page) to an even address page(target page) or from an even address page(source page) to an odd address page(target page). therefore, the copy-back program is permitted just between odd address pages or even address pages. 3. two-plane copy-back page program into plane 0&2(or plane 0&3, or plane 1&2, or plane 1&3) is prohibited. 4 . any command between 11h and 81h is prohibited except 70h and ffh.
flash memory 44 k9wag08u1b advance samsung confidential k9k8g08u0b figure 16. two-plane copy-back program operation with random data input r/b 85h 11h t dbsy add.(5cycles) data 85h data i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 add.(2cycles) 00h r/b add.(5cycles) t r source address on plane0 35h i/ox col. add.1,2 & row add.1,2,3 00h add.(5cycles) source address on plane1 35h col. add.1,2 & row add.1,2,3 t r 1 r/b 81h 10h t prog add.(5cycles) data 85h data i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 add.(2cycles) 1 2 2 destination address a 0 ~ a 11 : valid a 12 ~ a 17 : fixed ?low? a 18 : fixed ?low? a 19 ~ a 29 : fixed ?low? a 30 : valid destination address a 0 ~ a 11 : valid a 12 ~ a 17 : valid a 18 : fixed ?high? a 19 ~ a 29 : valid a 30 : must be same as previous a 30 note : 1. copy-back program operation is allowed only within the same memory plane. 2. on the same plane, it?s prohibited to operat e copy-back program from an odd address page(source page) to an even address page(target page) or from an even address page(source page) to an odd address page(target page). therefore, the copy-back program is permitted just between odd address pages or even address pages. 3 . any command between 11h and 81h is prohibited except 70h and ffh. note4 data output data output
flash memory 45 k9wag08u1b advance samsung confidential k9k8g08u0b read status the device contains a status register whic h may be read to find out whether program or erase operation is completed, and whethe r the program or erase operation is completed successfully. af ter writing 70h command to the co mmand register, a read cycle outpu ts the content of the status register to the i/o pins on the falling edge of ce or re , whichever occurs last. th is two line control allows the system to poll the progress of each device in multiple memory connections even when r/b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 2 fo r specific status register definitions. the command register remains in status read mode until further commands are issued to i t. therefore, if the status register is read during a random read cycle, the read command(00h) should be given before starting read cycles. table 2. status register definition for 70h command note : 1. i/os defined ?not use? are recommended to be masked out when read status is being executed. 2. status register definition for f1h & f2h command is same as that of 70h command. i/o page program block erase read definition i/o 0 pass/fail pass/fail not use pass : "0" fail : "1" i/o 1 not use not use not use don?t -cared i/o 2 not use not use not use don?t -cared i/o 3 not use not use not use don?t -cared i/o 4 not use not use not use don?t -cared i/o 5 not use not use not use don?t -cared i/o 6 ready/busy ready/busy ready/busy busy : "0" ready : "1" i/o 7 write protect write protect w rite protect protected : "0" not protected : "1" table 3. read status register definition for f1h/f2h command note : 1. i/os defined ?not use? are recommended to be masked out when read status is being executed. i/o no. page program block erase read definition i/o 0 chip pass/fail chip pass/fail not use pass : "0" fail : "1" i/o 1 plane0 pass/fail plane0 pass/fail not use pass : "0" fail : "1" i/o 2 plane1 pass/fail plane1 pass/fail not use pass : "0" fail : "1" i/o 3 not use not use not use don?t -cared i/o 4 not use not use not use don?t -cared i/o 5 not use not use not use don?t -cared i/o 6 ready/busy ready/busy ready/busy b usy : "0" ready : "1" i/o 7 write protect write protect write protect prote cted : "0" not protected : "1"
flash memory 46 k9wag08u1b advance samsung confidential k9k8g08u0b figure 17. read id operation ce cle i/o x ale re we 90h 00h address. 1cycle maker code device code t cea t ar t rea read id the device contains a product identification mode, initiated by wr iting 90h to the command register, followed by an address inp ut of 00h. five read cycles sequentially output the manufacturer code(e ch), and the device code and 3rd, 4th, 5th cycle id respective ly. the command register remains in read id mode until further commands are issued to it. figure 17 shows the operation sequence. figure 18. reset operation reset the device offers a reset feature, executed by writing ffh to t he command register. when the device is in busy state during ran dom read, program or erase mode, the reset operation will abort these operations. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the command register is cleared to wait for the next command, and the status register is cleared to value c0h when wp is high. if the device is already in reset state a new reset command will be accepted by the command register. the r/b pin transitions to low for trst after the reset command is written. refer to figure 18 below. ffh i/o x r/b t rst t whr t clr ech device 4th cyc. code 3rd cyc. 5th cyc. table 4. device status after power-up after reset operation mode 00h command is latched waiting for next command device device code(2nd cycle) 3rd cycle 4th cycle 5th cycle k9k8g08u0b dch 51h 95h 58h k9wag08u1b same as k9k8g08u0b
flash memory 47 k9wag08u1b advance samsung confidential k9k8g08u0b ready/busy the device has a r/b output that provides a hardware method of indicating the completion of a page program, erase and random read completion. the r/b pin is normally high but transitions to low after pr ogram or erase command is written to the command regis- ter or random read is started after address loading. it returns to high when the internal contro ller has finished the operation . the pin is an open-drain driver thereby allowing two or more r/b outputs to be or-tied. because pull-up resistor value is related to tr(r/b ) and current drain during busy(ibusy) , an appropriate value can be obt ained with the following reference chart(fig.19). its value can be determined by the following guidance. v cc r/b open drain output device gnd rp figure 19. rp vs tr ,tf & rp vs ibusy ibusy busy ready vcc voh tf tr vol where i l is the sum of the input currents of all devices tied to the r/b pin. rp value guidance rp(max) is determined by maximu m permissible limit of tr rp(min, 3.3v part) = v cc (max.) - v ol (max.) i ol + i l = 3.2v 8ma + i l 3.3v device - v ol : 0.4v, v oh : 2.4v c l tr,tf [s] ibusy [a] rp(ohm) ibusy tr @ vcc = 3.3v, ta = 25 c , c l = 50pf 1k 2k 3k 4k 100n 200n 2m 1m 50 tf 100 150 200 3.6 3.6 3.6 3.6 2.4 1.2 0.8 0.6
flash memory 48 k9wag08u1b advance samsung confidential k9k8g08u0b data protection & power up sequence the device is designed to offer protection from any involuntar y program/erase during power-transitions. an internal voltage det ector disables all functions whenever vcc is below about 2v(3.3v device). wp pin provides hardware protection and is recommended to be kept at v il during power-up and power-down. a recovery time of minimum 100 s is required before internal circuit gets ready for any command sequences as shown in figure 20. the two step command se quence for program/erase provi des additional software pro- tection. figure 20. ac waveforms for power transition v cc wp high we ready/busy 5 ms max operation note :during the initialization, the device consumes a maximum current of 30ma (i cc 1) 100 s ~ 2.3v ~ 2.3v invalid don?t care don?t care

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